Objective

RISC-V is the processor of choice after Intel x86 and ARM processor. RISC-V is an open core and is fully configurable to support a wide scope of applications with varying performance requirements. This course will cover basic processor design. RISC-V instruction set architecture will be described along with an elementary pipelined implementation. Based on the elementary design, different techniques to increase performance will be examined from different levels of cache to instruction level and data level parallelism. This course can be seen as a computer organization course based on RISC-V.

RISC-V 是繼 Intel x86 和 ARM 處理器之後的首選處理器。 RISC-V 是一個開放核心，完全可配置，可支援具有不同效能要求的廣泛應用。本課程將涵蓋基本的處理器設計。將描述 RISC-V 指令集架構以及基本的管線實作。基於基本設計，將從不同層級的快取到指令級和資料級並行性研究提高效能的不同技術。本課程可視為一門基於RISC-V的電腦組成課程。

Syllabus

Basic Computer Organization
RISC-V ISA
RISC-V Pipelined Datapath
Instruction Hazards
Memory Organization and Cache
Virtual Memory
Instruction Level Parallelism
Data Level Parallelism

Learning Outcome

1. Understand the basic concept of computer organization
2. Understand RISC-V ISA and appreciate the merit of different control implementations
3. Use memory organization to increase performance
4. Use different levels of parallelism to increase performance
5. Gain ability to configure a RISC-V

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