CHOY Chiu-sing, Oliver Professor B.Sc., M.Sc., Ph.D. (Manchester), C.Eng., MHKIE, MIEE, SrMIEEE Email: cschoy@ee.cuhk.edu.hk Telephone: +852 2609-8280

Resume of career:

Chiu-sing Choy received his B.Sc., M.Sc. and Ph.D. from the University of Manchester in 1983, 1984 and 1987 respectively, major in electrical and electronics engineering. From 1985, he spent a year in Ferranti Microelectronics, Oldham, U.K., assisting research in ASIC technology. In 1986, he joined Department of Electronic Engineering, The Chinese University of Hong Kong. When ASIC was still a novel idea to the local industry, he introduced an ASIC course into the undergraduate programme and initiated research into ASIC and VLSI designs. The then established VLSI/ASIC design laboratory is now fully equipped with industrial standard design tools and many sophisticated testing equipment. He is also active in the academic and professional circles. He has been external examiner for the Open University and thesis examiner for sister institutions. He is currently a member of the Community Service Committee and the Training Review Sub-committee of HKIE.


Current Research Interests:

Low Power High Speed Asynchronous Designs, Smart Card Technology and Applications, Digital Transceiver for 3rd Generation Mobile Communication, Encryption and Channel Coding Core designs


Current and Future Projects:

· Asynchronous Java Processor for Contactless Smart Card

· Low Power Asynchronous Design for Channel Coding in 3G Mobile Communication

· Low-power Asynchronous Elliptic Curve Cryptosystem with application to smart cards

· A CMOS Direct Conversion Receiver for Third Generation Mobile Communication

· On-Chip Antenna for Contactless Smart Card

· Low Power Mixed-Technique based on Static and Dynamic Logic for Asynchronous Designs

· Application Specific Instruction-set Processor with Asynchronous Methodology

· Framework for Active Smart Cards


Undergraduate Final Year Projects 2001/2002:

· A Paper-like Address book

· Mobile Applications for Palm Computing

· Smart Card Reader Module for Handspring Visor

· TD-PSOLA Cantonese Synthesizer

· ASIC Implementation of Convolutional Encoder For 3G Communication Systems Using Asynchronous Semi-Micropipeline Architecture

· Technology Re-mapping of Asynchronous Multiplier


Selected Publications:

· C.S. Choy, M.H. Ku and C.F. Chan, "A Low Power-noise Output Driver with Adaptive Characteristic Applicable to a Wide Range of Loading Conditions," IEEE Journal of Solid-State Circuits, vol. 32, no. 6, pp. 913-917, June 1997.

· V.W.Y. Sit, C.S. Choy and C.F. Chan, "A Four-phase Handshaking Asynchronous Static RAM Design for Self-timed Systems", IEEE Journal of Solid-State Circuits, vol. 34, no. 1, pp. 90-96, January 1999.

· T.C. Pang, C.S. Choy, C.F. Chan and W.K. Cham, "A Self-timed ICT Chip for Image Coding", IEEE Transactions on Circuits and Systems on Video Technology, vol. 9, no. 6, pp. 856-860, September 1999.

· J. Butas, C.S. Choy, J. Povazanec and C.F. Chan, "Asynchronous Cross-Pipelined Multiplier", IEEE Journal of Solid-State Circuits, vol. 36, no. 8, pp. 1272-1275, August 2001.

· J. L. Yang, C.S. Choy and C.F. Chan, "A Self-Timed Divider Using a New Fast and Robust Pipeline Scheme", IEEE Journal of Solid-State Circuits, vol. 36, no. 6, pp. 917-923, June 2001.

· C.S. Choy, J. Povazanec, J. Butas and C.F. Chan, "A New Control Circuit for Asynchronous Micro-Pipelines", IEEE Transactions on Computers, vol. 50, no. 9, pp. 992-997, September 2001.