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CHOY Chiu-sing, Oliver Professor B.Sc., M.Sc., Ph.D. (Manchester), C.Eng., FHKIE, MIEE, SrMIEEE Telephone: +852 3943-8280 |
Resume of career:
Professor Chiu-sing Choy received his B.Sc., M.Sc. and Ph.D. from the University of Manchester in 1983, 1984 and 1987 respectively, major in electrical and electronics engineering. From 1985, he spent a year in Ferranti Microelectronics, Oldham, U.K., participating in ASIC technology research. In 1986, he joined Department of Electronic Engineering, The Chinese University of Hong Kong, where he is presently a Professor.
Prof. Choy is a fellow of HKIE. He was the chairperson the Electronics Division in 2006/07 and was a council member of HKIE. Prof. Choy is active in supporting the local electronics industry. He led a number of ITF supported industry projects in optical pick-up designs, RFID technology and Structured ASIC. Prof. Choy published widely with over hundred of papers to his credit. He serves in many international conferences and is at present a member of the steering committee of ASP-DAC, the Co-chair of the International Symposium on Applied Reconfigurable Computing 2012, and the publication chair of VLSI-SoC 2011.
Current Research Interests:
Network-on-Chip, Body Area Network, Structured ASIC, Asynchronous Communication Links, OFDM-UWB Digital Transceiver, Real-time Object Detection.
Current Projects:
· A Simulation-oriented Channel Model for In- and On-body Communication
· Energy Optimization Methodology for In- and On-body Communication
· Asynchronous Network-on-Chip Design
· Real-time Pedestrian Detection System Implementation with FPGA
· Hand Contact Audio Reception Based on Intra-body Communication
Selected Publications:
· C.S. Choy, M.H. Ku and C.F. Chan, "A Low Power-noise Output Driver with Adaptive Characteristic Applicable to a Wide Range of Loading Conditions," IEEE Journal of Solid-State Circuits, vol. 32, no. 6, pp. 913-917, June 1997.
· V.W.Y. Sit, C.S. Choy and C.F. Chan, "A Four-phase Handshaking Asynchronous Static RAM Design for Self-timed Systems", IEEE Journal of Solid-State Circuits, vol. 34, no. 1, pp. 90-96, January 1999.
· T.C. Pang, C.S. Choy, C.F. Chan and W.K. Cham, "A Self-timed ICT Chip for Image Coding", IEEE Transactions on Circuits and Systems on Video Technology, vol. 9, no. 6, pp. 856-860, September 1999.
· J. Butas, C.S. Choy, J. Povazanec and C.F. Chan, "Asynchronous Cross-Pipelined Multiplier", IEEE Journal of Solid-State Circuits, vol. 36, no. 8, pp. 1272-1275, August 2001.
· J. L. Yang, C.S. Choy and C.F. Chan, "A Self-Timed Divider Using a New Fast and Robust Pipeline Scheme", IEEE Journal of Solid-State Circuits, vol. 36, no. 6, pp. 917-923, June 2001.
· C.S. Choy, J. Povazanec, J. Butas and C.F. Chan, "A New Control Circuit for Asynchronous Micro-Pipelines", IEEE Transactions on Computers, vol. 50, no. 9, pp. 992-997, September 2001.
· K. Xu and C.S. Choy, .A Power-efficient and Self-adaptive Prediction Engine for H.264/AVC Decoding,. IEEE Transactions on VLSI Systems, vol. 16, no. 3, pp. 302-313, March 2008.
· S.K. Tang, K.P. Pun, C.S. Choy, C.F. Chan and K.N. Leung, .A Fully Differential Band-Selective Low-Noise Amplifier for MB-OFDM UWB Receivers,. IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 55, no. 7, pp. 653-657, July 2008.
· C.F. Chan, K.P. Pun, K.N. Leung, J.P. Guo, L.K. Leung and C.S. Choy, .Low-Power Continuously-Calibrated Clock Recovery Circuit for UHF RFID EPC Class-1 Generation-2 Transponders,. IEEE Journal of Solid-State Circuits, vol. 45, no. 3, pp. 587-599, March 2010.
· M. Zhang and C.S. Choy, .Low-Cost Allocator Implementations for Networks-on-Chip Routers,. Journal of VLSI Design, 2010.
· W. Fan and C.S Choy, .Robust, Low-Complexity and Energy Efficient Dowlink Baseband Receiver Design for MB-OFDM UWB System,. IEEE Transactions of CAS I, vol.59, no. 2, pp. 399-408, Feb. 2011.
· M.H. Ho, Y.Q. Ai, T.C.P. Chau, S.C.L. Yuen, C.S. Choy, P.H.W. Leong and K.P. Pun, .Architecture and Design Flow for a Highly Efficient Structured ASIC,. IEEE Transactions on VLSI Systems, 2012.